This invention relates to circuitry for converting differential data signals to single-ended data signals with low jitter.
Differential signaling arrangements are used in a variety of environments such as in high-speed communications links. Differential signaling arrangements are generally more immune to noise than single-ended signaling schemes and can support higher data rates. In a differential arrangement, data is conveyed as complementary positive and negative signals. The positive and negative complementary signals are referenced to each other. In single-ended signaling arrangements, the same data may be represented by a single signal that is referenced to ground.
Digital integrated circuits generally use single-ended logic schemes internally. When high-speed differential digital data is received from a high-speed differential communications link, it is necessary to use a conversion circuit to convert differential data to single-ended data.
As semiconductor fabrication technology advances, it is becoming possible to fabricate differential-to-single-ended conversion circuits from metal-oxide-semiconductor (MOS) transistors with increasingly short gate lengths. However, conventional differential-to-single-ended conversion circuits that are formed from MOS transistors with short gate lengths are sensitive to the run lengths of incoming data signals, which leads to excessive jitter.
It would therefore be desirable to be able to provide improved differential-to-single-ended conversion circuits.